Semi Doped

New episode: Advanced packaging for AI chips, from wire bonds to TSMC CoWOS and Intel EMIB.
Packaging is no longer an afterthought. It is the chip, and Intel's EMIB challenges TSMC's CoWOS.
Three CoWOS flavors: silicon, organic RDL, local bridges
EMIB embeds tiny bridges into the substrate, no interposer
EMIB-T and EMIB-M add through-silicon vias and power capacitors
Google is booking 3M TPUs on EMIB via MediaTek by 2028
Package sizes keep climbing: 5.5x reticle today, 40x ahead
This episode is brought to you by SambaNova. Try SambaNova's fast inference today at the SambaNova Dashboard!
Connect with Vik and Austin via a daily free newsletter:
https://www.semidoped.com

Vik's Paid Substack: https://www.viksnewsletter.com
Austin's Paid Substack: https://www.chipstrat.com
Chapters:
(0:00) "There Is No Chip Without the Packaging"
(0:28) Intro and SpaceX IPO Day
(5:15) What We're Covering: CoWOS, EMIB, Google
(7:40) Simple Packaging: Wire Bonds to Flip Chip
(17:07) What Makes Packaging "Advanced"
(33:44) CoWOS: Three Flavors Explained
(45:30) EMIB: Intel's Embedded Bridge Approach
(52:47) EMIB-T and EMIB-M
(57:31) CoWOS vs. EMIB Trade-offs
(1:02:18) Google's 3M TPU EMIB Order

Austin and Vik discuss their recent experience at Computex, where they met for the first time in person after six months of podcasting together.

They share insights about the massive show, the people they connected with, and the exciting developments in AI hardware and interconnect technology.

Connect with Vik and Austin via a daily free newsletter:
https://www.semidoped.com

Vik's Paid Substack: https://www.viksnewsletter.com
Austin's Paid Substack: https://www.chipstrat.com

Chapters

00:00 Meeting in Person for the First Time
03:05 Experiencing Computex: A Massive Show
05:17 Connecting with the Audience: Real-Life Encounters
06:46 Networking with Industry Leaders
10:42 Keynote Highlights: Marvell's Vision
15:11 The Future of Interconnects: CPO and Beyond
22:54 Exploring Optical Interconnects and Future Technologies
25:56 Micro LED Developments and Future Conferences
27:34 Power Innovations in Data Centers
30:54 Intel's Keynote and New CPU Technologies
36:31 Intel Foundry's Advancements and Industry Implications

Huawei dropped a paper claiming 1.4nm-class performance without EUV, and the internet immediately declared ASML dead and US export controls useless. Austin and Vik recorded one day after Memorial Day to unpack what Huawei actually announced at ISCAS 2026 — and why the "EUV killer" headline gets the story backwards.

They walk through the tau scaling law (tau is delay, and the idea is to attack it at the system level instead of the transistor), logic folding via hybrid bonding, the Kirin 2026 that doubles transistor count without shrinking, and who can actually manufacture stacked logic. Then the other tau knobs: a unified memory bus and near-packaged optics. Along the way: BESI vs EV Group, die-to-wafer vs wafer-to-wafer bonding, and why hybrid bonding isn't export-controlled the way EUV is.

The takeaway is the opposite of the headline. Tau scaling is rational engineering under constraint, it's bullish for ASML (two DUV wafers per product, not fewer), and the moment EUV-enabled fabs stack their own advanced-node wafers, the gap widens instead of narrowing. Bullish advanced packaging, bullish EDA and multiphysics.

Chapters:
0:00 The "EUV killer" paper that broke the internet
2:28 What Huawei actually announced at ISCAS
4:00 Tau scaling: optimize delay, not transistors
8:58 The equation and the 10x AI claim
11:05 Logic folding: stacking logic on logic
17:24 Who builds it, and can hybrid bonding be banned?
24:16 Why this is bullish for ASML
29:49 The other tau knobs: memory and optics
35:18 Takeaways: packaging, EDA, multiphysics

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Spend one hour here and you've caught up on the entire arc of semiconductor lithography. Austin and Vik run a masterclass on the technology that decides who gets to make leading-edge chips, and why so few companies can afford to.
The thread is economics. An EUV machine runs about $400 million, a new fab needs roughly 15 of them, and the total bill clears $20-30 billion before a single wafer ships. Austin and Vik trace the whole story: Rock's Law and the cost of a fab, what it actually takes to build one, the evolution from 193nm DUV through multi-patterning to 13.5nm EUV, how ASML generates EUV light by exploding falling tin droplets, and the move to high NA and its mirrors. Along the way, the fun history — i-line, krypton fluoride, immersion lithography, and the engineer who started it all by flipping a microscope upside down.
Then the part that matters most: where lithography goes next. Two startups, xLight and Substrate, are attacking the cost problem from first principles. xLight wants to decouple the light source from the scanner with a free-electron laser and sell photons as a service. Substrate wants to skip EUV entirely and revive X-ray lithography. If either works, the economics of who can build a fab change completely.
Chapters:
 0:00 The 13F panic, and today's topic
 2:23 Why the real story is economics, not physics
 6:18 Austin in the clean room: graphene and bunny suits
 10:06 Rock's Law and the $20 billion fab
 18:08 DUV, the Sharpie, and a history of light
 24:58 Multi-patterning, explained with a football field
 34:45 How EUV makes 13.5nm light from tin droplets
 41:14 High NA, anamorphic optics, and the half-field tax
 46:45 The startups rethinking lithography: xLight and Substrate
Relevant reading:
 Chipstrat — The economics of lithography: https://www.chipstrat.com/p/lithography-economics
Chipstrat — xLight and photons as a service: https://www.chipstrat.com/p/photons-as-a-service
Chipstrat — Substrate and X-ray lithography: https://www.chipstrat.com/p/substrate
Vik's Newsletter — the viability of X-ray lithography: https://www.viksnewsletter.com/p/an-in-depth-look-at-the-viability
Fred Chen — LELE multipatterning and EUV stochastics (Substack): https://frederickchen.substack.com/p/can-lele-multipatterning-help-against
Chip War, Chris Miller
Focus, Marc Hijink (the ASML book): https://www.amazon.com/Focus-Inside-struggle-complex-machine-ebook/dp/B0CW1FLCD4
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Cerebras IPO is the only thing to talk about this week. 🔥
IPO prices at $185/share. Pops nearly 70% right after. The first wafer-scale chip company to make it public — after a 40-year curse killed every prior attempt.
A water-cooler-style convo on what Cerebras actually builds, why a 23 kW wafer is a power and cooling nightmare, why 44 GB of SRAM is both the magic and the wall for LLM inference, and the cursed Trilogy Systems saga that Gene Amdahl tried — and failed — to pull off in 1983.
Why does Cerebras leave the whole wafer intact instead of dicing it? How do they route around defects to harvest ~900K working cores out of ~1M? Why is power delivery vertical, and why does the wafer literally expand a tenth of a millimeter when it heats up? What does the OpenAI deal actually buy — wafers, or tokens? And why does that distinction matter?
Chapters:
 0:00 Cold open: 23 kW per wafer
 0:15 Cerebras IPO day at $185
 2:39 What's a wafer-scale engine
 10:30 Power, cooling, and thermal expansion
 18:12 The 44 GB wall
 26:35 The Trilogy Systems curse
 32:11 Supercomputing → training → inference
 39:36 The OpenAI deal and the Wild West
Relevant reading:
 Vik's Substack post on the Cerebras IPO and OpenAI deal: https://www.viksnewsletter.com/
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X: https://x.com/vikramskr
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